1. Field of the Invention
The present invention relates to a multiple-port network interface circuit and related controlling method, and more particularly, to a multiple-port network interface circuit capable of transmitting a plurality of signals to access points, like terminals, over a network via a plurality of embedded ports. The network interface circuit triggers signal transmissions on the embedded ports with a variety of clocks of different phases to guarantee that data transmissions for the signals on the ports will not proceed simultaneously for improving power bounce and cross-talk.
2. Description of the Prior Art
In the modern information age, the Internet, capable of exchanging information, data, and knowledge efficiently, is becoming a very popular tool to develop new technologies and to improve relations among people. That is why it has become a major concern for information industry as well as government to develop any facilities related to the Internet as fast and thoroughly as possible.
A variety of network connection topologies have been used to build a network formed with a plurality of terminals. Each of the terminals in these topologies can be deemed as a node of the network and connections between these nodes, directly and indirectly, make up the network. For example, 10 BASE T and 100 BASE T, two popular patterns of local area networks, both adopt a star-structured topology to build a network, each of the terminals connecting to the rest of the nodes or to another network device (hubs, switches, or routers) via a hub or a switch to form a network and to exchange data with network-related devices in the network. In other words, a network-related device, such as the hub, switch, and router, interconnects with the nodes (terminals) to form a network so that users of any terminal can access data of the rest of the terminals via the network.
These network-related devices used to interconnect the nodes in the network usually comprise network connection ports through which data can be exchanged among the nodes, each network connection port being connected to only one node. These network devices can, therefore, transmit data signals with a network interface circuit to each of the network nodes via a corresponding network connection port and receive data transmitted from the network nodes, thus realizing inter-network connection. Please refer to FIG. 1, which is a function block diagram of a multiple-port network interface circuit 10 according to the prior art. The network interface circuit 10 can be a network interface circuit installed in a network device such as a hub, a switch or a router. In this embodiment, the network interface circuit 10 is assumed to be an eight-ported network interface. The eight ports of the eight-ported network interface circuit 10 are respectively connected to eight network nodes 19A through 19H (such as terminals or other network devices, like a computer, a network printer, a hub, or a switch). The network interface circuit 10 can transmit data to and receive data from the eight nodes simultaneously. The network interface circuit 10 comprises a medium access control (MAC) circuit 12 and a physical layer (PHY) circuit 14 for respectively accessing a MAC layer and a PHY layer in an open system interconnection (OSI) structure. The PHY circuit 14 comprises eight signal circuits 16A through 16H, which respectively corresponds to the eight nodes 19A through 19H, and is respectively connected to eight signal ports Sp1 through Sp8 for managing data ready to be respectively transmitted to the nodes 19A through 19H and for respectively forming corresponding signals mp1 through mp8 and respectively transmitting these signals mp1 through mp8 to the nodes 19A through 19H via corresponding transmission ports 22A through 22H. The signals transmitted from the nodes from 19A through 19H to the network interface circuit 10 are then further transmitted to a receiving circuit 18 via corresponding receiving ports 24A through 24H and to the MAC circuit 12. In other words, the transmission port 22A and the receiving port 24A combine to form a network connection port capable of accessing data of the node 19A in a duplex manner. Similarly, the transmission port 22B and the receiving port 24B combine to form another network port of the network interface circuit 10 to access data of the node 19B, and so on.
In addition to the signal circuits 16A through 16H used to manage signal transmission and signal circuit 18 used for signal reception, the PHY circuit 14 further comprises a clock generator 20 for generating a clock CLK0 to coordinate operations of each of the function blocks in the PHY circuit 14, especially of the signal circuits 16A through 16H. Correspondingly, each of the signal circuits 16A through 16H also comprises a clock end 25 for receiving the clock CLK0 and operating accordingly. The clock generator 20 can be a phase-locked loop, which is electrically connected to the MAC circuit 12 for generating the clock CLK0 according to a reference clock CLKr0, which is generated by the MAC circuit 12. In other words, by controlling the reference clock CLKr0, the MAC circuit 12 is capable of controlling operation clocks of the PHY circuit 14, especially timing sequences of the nodes 19A through 19H. The clock generator 20, as a phase-locked loop, further comprises a phase detector PD0, a charge pump CP0, an oscillator VCO0, and/or a frequency divider DIV0. The phase detector PD0 detects frequency and phase differences between the reference clock CLKr0 and an oscillating clock CLKd0 and generates an error signal Se0. The charge pump CP0 transforms the error signal Se0 to a control signal Sc0 for controlling a voltage. For example, the charge pump CP0 can control currents flowing through a current source with the error signal Se0 and charges the currents into a capacitor to generate the control signal Sc0. The oscillator VCO0 generates the oscillating clock CLK0 and adjusts frequency of the oscillating clock CLK0 according to the control signal Sc0. The frequency divider DIV0 divides the clock CLK0 and generates an oscillating clock CLKd0, which is then fed back to the phase detector PD0 such that the clock generator 20 can adjust frequency of the clock CLK0 again according to the frequency and phase differences between the oscillating clock CLKd0 and reference clock CLKr0. Therefore, the clock CLK0 and the reference clock CLKr0 generated by the MAC circuit 12 is synchronized.
The operations of the MAC circuit 12 and the PHY circuit 14 are described as follows: The MAC circuit 12 packets data transmitted from the network interface circuit 10 to the nodes 19A through 19H and forms corresponding packets to be transmitted over a network. That is, for example, the MAC circuit 12 appends a header, an error check code, and an address, like a MAC address, of related physical apparatus to data. Packets ready to be transmitted to the nodes 19A through 19H are respectively transmitted to corresponding signal circuits 16A through 16H (the packet transmitted to the network node 19A is managed by the signal circuit 16A) and are managed by the corresponding signal circuits 16A through 16H with certain processes, such as scrambling, encoding and modulating, and signal driving. Then the processed packets can be transmitted from corresponding transmission ports to the nodes via transmission lines with stronger driving capability and better signal shape. Signals transmitted from the network nodes to the network interface circuit 10 are then received and decoded, de-scrambled or demodulated back to the original packets by the receiving circuit 18 and are transmitted back to the MAC circuit 12, which acquires data stored in these packets. Practically, the signals mp1 through mp8 transmitted to the nodes are transmitted to corresponding nodes in a differential form through transmission lines such as twisted-paired lines. Likewise, each of the network nodes transmits two signals opposite to each other to corresponding receiving ports 24A through 24H of the network interface circuit 10.
Please refer to FIG. 2 as well as to FIG. 1. FIG. 2 is a timing diagram of the clock CLK0 and signals mp1 through mp8 transmitted over the transmission ports 22A through 22H of the network interface circuit 10 according to the prior art, with a horizontal axis representing time and a vertical axis representing levels of the signals mp1 through mp8. In this embodiment, the signal circuits 16A through 16H are assumed to be rising-edge-triggered signal circuits. That is, as each of the signal circuits receives a triggering clock, the signal circuit manages corresponding signal processes and generates data at a moment corresponding to the rising edge of the triggering clock. As FIG. 1 shows, the signal circuits 16A through 16H are all triggered by the clock CLK0 simultaneously and the signals mp1 through mp8 may proceed with data transitions at the same time, changing from one data pattern to another. For example, as shown in FIG. 2, the clock CLK0 rises from a low level up to a high level at a time tp0 and generates a rising edge concurrently, and a data “0” transmitted with the signal mp1 is transformed into a data “1” at the time tp0. Likewise, the signal mp1 will be transformed from a first data “1” to a second data “0” at a time corresponding to another rising edge of the clock CLK0 at a time tp1. In the network interface circuit 10, because the signal circuits 16A through 16H are all triggered by an identical clock, clock CLK0, the signals mp1 through mp8 transmitted by the signal circuits proceed the data transition at the same time. As shown in FIG. 2, each of the signals mp1 through mp8 transform a data “0” to another data “1” at a time corresponding to a rising edge at time tp0, signals mp3 through mp8 transform a data “1” to another data “0” at a time corresponding to a rising edge at time tp8, and signals mp1 through mp6 transform a data “1” to another data “0” at a time corresponding to a rising edge at time tp11, and so on.
As known by those skilled in the art, the signal circuits 16A through 16H, if not having enough driving capability, cannot transmit the signals mp1 through mp8 respectively to the corresponding remote network nodes 19A through 19H. For example, a data transition of the signal circuit 16A at time tp0 for transmitting a data “0” and then a data “1” to the network node 19A can only happen at a moment when the signal circuit 16A has the capability to drive a transmission line connected between the transmission port 22A and the network node 19A with great enough current, and a voltage level of the transmission line transitions from a low voltage level of the data “0” to a high voltage level of the data “1”. As soon as the voltage level of the transmission line is raised to the high voltage level, the burden on the signal circuit 16A to drive signals can be released and the transmission line can be kept at the high voltage level with only a small power. For example, no data transitions happen at time tpA and the PHY circuit 14 consumes little power, resulting in no power bounce. On the contrary, the signal circuit 16A cannot drop a voltage level of the transmission from a high voltage to a low one with too little current. Likewise, the remaining signal circuits 16B through 16H can only proceed with data transition with currents which are great enough to drive signals to corresponding remote nodes via the transmission line. However, since the prior art network interface circuit 10 triggers the signal circuits 16A through 16H with the identical clock CLK0 simultaneously, the signal circuits draw huge power to proceed with the data transition at the same time. Demanding power to drive signals by the signal circuits simultaneously abruptly arises power-consumption of the PHY circuit 14, thus generating the power bounce. In general, the network interface circuit 10 is provided by an external direct power source to function. If the power requested by the signal circuits 16A through 16H of the network interface circuit 10 to drive the data transition raises simultaneously, the external direct bias source can only provide unstable power to the network interface circuit 10 and generates ripples in frequency response to affect the signal circuits 16A through 16H. In particular, as the network interface circuit 10 begins to function, the network interface circuit 10 sends link pulses to each of the network nodes and establishes synchronous connections to the network nodes. During the establishment of the connections, because the signals m1 through m8 proceed the data transition simultaneously and request power to drive the data transition accordingly, as indicated by a period in FIG. 2 from time tp0 to time tp7, even though data the signals m1 through m8 transmit in a moment are varied, two signals or more are still likely to drive the data transition simultaneously, such as the signals mp3 through mp8 do at time tp8, and the power bounce inevitably occurs.
In addition to the power bounce, the simultaneously triggered data transition occurring in the prior art network interface circuit 10 also generates cross-talk among the signal circuits and transmission lines. For example, since the signals m1 through m8 are transited from low levels to high levels at time tp0 simultaneously, part of the energy of the signal mp2 will couple to the signal mp1 because of an additive electricity coupling between the signal circuits 16A and 16B, so a real level of the signal mp1 is higher than an ideal level of the signal mp1, as indicated by dashed waveform 27a shown in FIG. 2. In other words, after climbing to a predetermined voltage level, which indicates a digital “1”, the signal mp1 continues climbing to a voltage level higher than the predetermined voltage level and probably damages the corresponding signal circuit. Likewise, the signal mp2 at time tp9 is transited from a high level to a low level and the signal mp3 from the low level to the high level. As the signal mp2 is pulled from the high level to the low level, part of the energy of the signal mp3 will couple the signal mp2 away from a voltage level substantially equal to zero volts (or take a long time to pull the signal mp2 down to zero voltages), as the dashed waveform 27b indicates. On the other hand, part of the energy of the signal mp2 will couple the signal mp3 to a voltage level lower than the high voltage level the ideal voltage level for the digital “1”, as indicated by a dashed waveform 27c shown in FIG. 2. As soon as the aforementioned distortion or delay problems happen, data misunderstanding (misunderstanding a digital “1” as a digital “0”) and the signals not being synchronous affect data transmission over a network.
In conclusion, the prior art network interface circuit 10 triggers signals ready to be transmitted to network nodes with an identical clock and gives the signals the data transition simultaneously, resulting in power bounce, cross-talk, the power provided by the network interface circuit 10 not being stable, and waveforms of the signals being distorted. In particular, it is becoming more and more critical to demand a high network data transmission rate in the modern information age, so the network interface circuit 10 needs more time to recover from an oscillating state to a stabilized one and aggravates the power bounce. Therefore, the signal circuits have to consume more power to drive the data transition, and the power bounce, electricity coupling, and waveform distortion due to the data transition become more and more apparent.